1. Field of the Invention
The present invention relates to a higher-order digital sigma-delta modulator for use in an oversampling type digital-to-analog converter (DA converter) and, more particularly, a limiter circuit for stabilizing an operation of the sigma-delta modulator.
2. Description of the Related Art
It is known that information of the original signal is not damaged if a sampling frequency is set twice as high as a signal frequency band f.sub.B based on the Nyquist's sampling theorem when an analog signal is encoded as digital data of sampling value. A sampling frequency f.sub.S of a commonly-used DA converter is therefore set to be 2.2 to 2.4 times as high as the signal frequency band f.sub.B.
An oversampling type DA converter has recently been developed and put to practical use in which the sampling frequency f.sub.S is set to be considerably higher than the signal frequency band f.sub.B to enhance conversion precision and increase an S/N (signal-to-noise) ratio. If the number of bits (resolution) is expressed by n, the maximal S/N ratio S/N.sub.max of a simple oversampling type DA converter is given by the following equation. EQU S/N.sub.max =(3/2)2.sup.2n (f.sub.S /2f.sub.B) . . . (1)
It is obvious from the above equation (1) that the S/N ratio is improved by 6 dB if the resolution n of the D/A converter is increased by one bit. Even if, however, the sampling frequency f.sub.S is doubled, the S/N ratio is improved by 3 dB only.
Various methods for sufficiently increasing an S/N ratio without heightening the sampling frequency f.sub.S are developed. One of the methods is to use a DA converter having a first order sigma-delta modulator, which is, for example, disclosed in Toshio Misawa et al., "Single-Chip per Channel Codec With Filters Utilizing .SIGMA.-.DELTA. Modulation," IEEE Journal of Solid-State Circuits, Vol. SC-16, No. 4, August, 1981, pp. 333-341.
This DA converter has transmission characteristics expressed by the following equation. EQU Y(z)=X(z)+(1-z.sup.-1)E(z) . . . (2)
In the equation (2), a quantization error E(z) is not usually correlated with an input signal X(z), and the frequency characteristics are flat, so that the noise frequency characteristics are given as follows if a clock period is T. EQU (1-e.sup.j.omega.T).apprxeq.j.omega.T . . . (3)
where .omega.T&lt;&lt;1. Since noise is proportionate to frequency, if the signal frequency band f.sub.B is considerably made lower than the sampling frequency f.sub.S, the S/N ratio is improved by 9 dB in a signal band every time the sampling frequency f.sub.S is doubled.
A one-bit DA converter having a higher-order sigma-delta modulator is disclosed in Stuart K. Tewksbury et al., "Oversampled, Linear Predictive and Noise-Shaping Coders of Order N&gt;1," IEEE Transactions on Circuits and Systems, Vol. Cas-25, No. 7, July, 1978, pp. 436-447; Kuniharu Uchimura et al., "VLSI A-to-D and D-to-A Converters with Multi-Stage Noise Shaping Modulators," ICASSP 86, Tokyo, pp. 1545-1548; and Yasuyuki Matsuya et al., "A Multi-Stage Noise Shaping 16 bit CMOS D to A conversion LSI", Journal of Institute of Electronic Information Communications, Report on Technical Research into Applied Acoustics, EA-87-79, 1987, pp. 25-32.
The DA converters disclosed in the above three publications basically include an n-stage integrator and differ from a first order sigma-delta modulator in that a feedback signal is supplied to the n-stage integrator. The transmission characteristics of the DA converters are represented by the following equation. EQU Y(z)=X(z)+(1-z.sup.-1).sup.n E(z) . . . (4)
If the degree of the higher-order sigma-delta modulator is n, the S/N ratio is improved by 3.times.(2n+1) dB in the signal band every time the sampling frequency f.sub.S is doubled, and it is also improved much more than using a DA converter having a primary sigma-delta modulator.
When a quantization level is binary (1 bit), the foregoing higher-order sigma-delta modulator needs a limiter circuit to prevent an oscillation mode from being set if the number of stages (n) of the integrator is two or more.
The DA converter including such a limiter circuit is disclosed in P.J.A. Naus et al., "A CMOS Stereo 16-bit D/A Converter For Digital Audio," IEEE Journal of Solid-State Circuits, Vol. Sc-22, No. 3, June, 1987, pp. 390-394. The limiter circuit disclosed in this publication comprises an inverter circuit, an exclusive-OR circuit, and a switch circuit, as shown in FIG. 1.
The limiter circuit shown in FIG. 1 limits data of 21 bits in length to data of 20 bits in length. A data line 90-1 of the most significant bit MSB in 21-bit data lines 90 is connected to one of input terminals of an exclusive-OR circuit 92, an input terminal of an inverter 91, and a data line 100-1 of the most significant bit MSB in 20-bit data lines 100. A data line 90-2 of significant bit 2SB is connected to the other input terminal of the exclusive-OR circuit 92. Data lines 90-3 to 90-21 of bits 3SB to LSB are connected to data lines 100-2 to 100-20 of bits 2SB to LSB through switch circuits SW1 to SW19, respectively. The switch circuits SW1 to SW19 each includes a transmission gate, a clocked inverter, and the like and are switched in response to signals output from the exclusive-OR circuit 92. An output terminal of the inverter 91 is connected to terminals H of the switch circuits SW1 to SW18, and a "1" level signal is supplied to a terminal H of the switch circuit SW19. The data lines 90-3 to 90-21 of the bits 3SB to LSB are connected to terminals L of the switch circuits SW1 to SW19, respectively. The switch circuits SW1 to SW19 are switched to the terminals H when the output signal of the exclusive-OR circuit 92 is "1" in level, and they are switched to the terminals L when the output signal is "0" in level.
In the arrangement described above, when both the data lines 90-1 and 90-2 of MSB and 2SB are "0" in level, the output signal of the exclusive-OR circuit 92 becomes "0" in level, and the switch circuits SW1 to SW19 are switched to the terminals L. The data lines 90-3 to 90-21 of 3SB to LSB are connected to the data lines 100-2 to 100-20 of 2SB to LSB, respectively. Data supplied to the data lines 90- and 90-3 to 90-21 is therefore transmitted to the data lines 100-1 to 100-20.
When the data line 90-1 of MSB is "0" in level and the data line of 2SB is "1" in level, the output signal of the exclusive-OR circuit 92 becomes "1" in level, and the switch circuits SW1 to SW19 are switched to the terminals H. A "1" level signal is supplied from the inverter 91 to the data lines 100-2 to 100-19 of 2SB to 19SB, and the "1" level signal is also supplied to the data line 100-20 of LSB. The data lines 100-2 to 100-20 are fixed to "1" in level, regardless of the level of data supplied to the data lines 90-3 to 90-21.
When the data line 90-1 of MSB is "1" in level and the data line 90-2 of 2SB is "0" in level, the output signal of the exclusive-OR circuit 92 becomes "1" in level, and the switch circuits SW1 to SW19 are switched to the terminals H. A "0" level signal is supplied from the inverter 91 to the data lines 100-2 to 100-19 of 2SB to 19SB, and a "1" level signal is supplied to the data line 100-20 of LSB. The data lines 100-2 to 100-19 are fixed to "0" in level and the data line 100-20 is fixed to "1" in level, regardless of the level of data supplied to the data lines 90-3 to 90-21.
When both the data lines 90-1 and 90-2 of MSB and 2SB are "1" in level, the output signal of the exclusive-OR circuit 92 becomes "0" in level, and the switch circuits SW1 to SW19 are switched to the terminals L. The data lines 90-3 to 90-21 of 3SB to LSB are connected to the data lines 100-21 to 100-20 of 2SB to LSB, and data supplied to the data lines 90-3 to 90-21 is transmitted to the data lines 100-2 to 100-20.
The transmission characteristics of the foregoing limiter circuit is shown in FIG. 2. As shown in FIG. 2, if an input exceeds a 20-bit full scale, an output is clamped by the 20-bit full scale and becomes constant.
The limiter circuit is relatively complicated and causes a delay of a considerably long period of time, however elaborately the circuit is formed. The sampling frequency f.sub.S cannot sufficiently be increased, and the improvement in S/N ratio is limited.